Pat Gelsinger joined Intel during a difficult time and did his best to revive the company before retiring, but as Intel CEO, Pat Gelsinger has yet to see his decision-making the results brought about. However, according to him, the 18A process technology – the culmination of five nodes in his four-year plan – was a success. After being ousted by the board, Gelsinger now has more time to respond to the news on X, which adds some color to the progress of Intel’s node development.
Pat Kissinger responds to Patrick Moorehead postal Claims rejected story about Broadcom Very disappointed with Intel 18A Called “fake news” due to low yields. The original story appeared in early September, just after the death of then-Intel CEO Pat Gelsinger Defect density (D0) of 18A disclosedwhich was 0.4 def/cm^2 at that time.
“I am extremely proud of the incredible work and progress the TD/18A team has made,” Kissinger wrote In X post.
Considering that 18A was still several quarters away from mass production at that time, this defect density was good enough, although it was worse than TSMC. For example, TSMC’s N7 and N5 processes have a defect density of about 0.33 def/cm2 in the first three-quarters of mass production, the same defect density as Intel’s 18A in early September.
It is generally believed that a The defect density is less than 0.5 defects per square centimeter. (0.5 def/cm^2), but when it comes to actual wafer throughput, everything depends on the wafer size.
Broadcom is known for its giant system-in-packages for AI, with computing wafers approaching the size of photomasks, 858 mm^2 in the case of EUV lithography tools. Let’s say we’re dealing with an 800 mm^2 die, which is the size of an Nvidia Blackwell GPU die (two die per B100/B200 processor). In this example, there are 59 – 65 candidates on 300 mm wafer (Assuming we are dealing with a hypothetical 23´34.8 mm mold), depends on various parameters. The defect density is 0.4 def/cm^2, which gives us Five perfect dies per wafer The output is approx. 9%. We have discussed 15 perfect wafers and yield at a defect density of 0.2 def/cm^2 24.9%.
There are several issues to be aware of in such calculations. First, both Broadcom and Nvidia have implemented huge redundancies into their designs so that even with relatively high defect densities, they can get enough available for sale Tools to justify using advanced nodes to produce 300mm wafers. Depending on the customer and contract, this could be $20,000 per wafer, which means their actual yields are much higher than what we get from publicly available yield calculators.
Second, not all processors are big. For example, Apple’s A18 Pro system single chip size for the iPhone 16 Pro smartphone is 105 mm^2, which is a very large processor for a consumer device. 105 mm^2 (assuming it is an 11´9 mm design) gives us 625 candidates per 300 mm wafer, and at a defect density of 0.4 def/cm^2 it gives us 587 Perfectly finished wafers, yielding 68.2%. Again, Apple likely implemented a lot of redundancy into its design, so actual yield available for sale The stakes are higher.
Overall, Intel said its 18A process technology is currently showing promising defect density numbers of 0.4 defects per square centimeter. Although this density is slightly higher than that of TSMC benchmark At comparable stages of development, it meets industry standards for advanced nodes and is sufficient to produce usable throughput based on die size and design redundancy. Larger wafers, such as Broadcom and Nvidia’s AI chiplets, face more significant yield challenges, but advanced redundancy technology may alleviate these issues, allowing for a sizable number of salable wafers. Meanwhile, smaller processors, such as Apple’s A18 Pro, can achieve significantly higher yields even at the same defect density.