Tachyum has released a 1,600-page guide for optimizing the performance of its Prodigy general-purpose processor FPGA hardware. While the company has yet to tapeout its Prodigy processor after years of delays, it has release Performance optimization manuals for chips with unique instruction set architectures and optimization strategies are provided before actual products are sampled or marketed.
The Prodigy general-purpose processor has faced repeated delays since its initial launch. Initially planned for tapeout in 2019 and launch in 2020, the schedule changed multiple times: from 2021 to 2022, then to 2023, and then to 2024. Will stream wafers by 2025, thus delaying Reference server sampling in the first quarter of next year. Although in form, the company still plans to launch Mass production of Prodigy processors in 2025it remains to be seen whether the company can complete all necessary milestones (tape out, debug, sample, start mass production) in just one year.
Tachuym’s Prodigy design features 192 customized 64-bit computing cores based on a new microarchitecture that is said to be equally suitable for general-purpose computing as well as highly parallel AI and HPC computing. In particular, ISA combines a wide range of vector and matrix instructions to solve problems in artificial intelligence and supercomputing applications, and new performance optimization guidelines include design guidelines for developing AI and HPC software.
The Prodigy instruction set architecture (ISA) combines elements of RISC and CISC designs; Tachyum said the ISA avoids the complex, lengthy and inefficient variable-length instructions common in traditional CISC processors. All instructions are standardized as 32 or 64 bits, and some instructions incorporate memory access capabilities to further improve performance.
Tachuym’s Prodigy FPGA has built-in performance counters for real-time monitoring and analysis of execution time events. The tools allow programmers and engineers to identify bottlenecks and optimize code for greater efficiency, making the processor ideal for demanding computing tasks, the company said.
The manual provides specific optimization techniques, including managing scheduling constraints, improving memory routines, aligning branches and instructions, and mitigating scratchpad forwarding challenges. In addition, it provides guidance on handling cache operations, load/store alignment, and accessing special registers, ensuring developers can fine-tune their software for optimal performance.
“Software programmers, test engineers, compiler developers, and systems and solutions engineers will appreciate the opportunity to learn more about how Prodigy provides inherent performance advantages for efficiently processing AI, cloud and HPC workloads,” said Dr. Radoslav Danilak. Founder and CEO of Tachyum. “Prodigy’s integrated capabilities will help users achieve industry-leading computing efficiency, gain insights faster, conduct research faster, and generate results faster.”
As usual, the evidence is in the shipping wafers, and Tachyum hasn’t even taped out the wafers yet.